1. Field of the Invention
The present invention relates to a memory cell capacitor and method for producing the same. More particularly, the present invention relates to a method of forming high dielectric constant memory cell capacitors which utilize relatively large surface area structures without electric field breakdown of the high dielectric constant material on the relatively large surface area structures.
2. State of the Art
A widely-utilized DRAM (Dynamic Random Access Memory) manufacturing process utilizes CMOS (Complimentary Metal Oxide Semiconductor) technology to produce DRAM circuits which comprise an array of unit memory cells, each including one capacitor and one transistor, such as a field effect transistor. In the most common circuit designs, one side of the transistor is connected to one side of the capacitor, the other side of the transistor and the transistor gate are connected to external circuit lines called the bit line and the word line, and the other side of the capacitor is connected to a reference voltage that is typically one-half the internal circuit voltage. In such memory cells, an electrical signal charge is stored in a storage node of the capacitor connected to the transistor that charges and discharges the circuit lines of the capacitor.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. The advantages of increased miniaturization of components include: reduced-bulk electronic equipment, improved reliability by reducing the number of solder or plug connections, lower assembly and packaging costs, and improved circuit performance. In pursuit of increased miniaturization, DRAM chips have been continually redesigned to achieve ever higher degrees of integration. However, as the dimensions of the DRAM chips are reduced while at the same time memory capacity is increased, the occupation area of each unit memory cell of the DRAM chips must be reduced. This reduction in occupied area necessarily results in a reduction of the dimensions of the cell capacitor, which, in turn, makes it difficult to ensure required storage capacitance for transmitting a desired signal without malfunction. However, the ability to densely pack the unit memory cells, while maintaining required capacitance levels, is a crucial requirement of semiconductor manufacturing if future generations of ever higher memory capacitor DRAM chips are to be successfully manufactured.
In order to minimize a decrease in storage capacitance caused by the reduced occupied area of the capacitor, the capacitor should have a relatively large surface area or a high dielectric constant dielectric layer in the capacitor. With regard to increasing capacitor surface area, there have been a variety of methods proposed for achieving this goal, including forming the capacitor such that various three-dimensional shapes extend therefrom. These three-dimensional shapes may include fins, cylinders, and boxes, as well as forming rough surfaces on these shapes.
With regard to the use of a high constant capacitor layer, the dielectric constant is a value characteristic of a material which is proportional to the amount of charge that can be stored in the material when it is interposed between two electrodes. High dielectric constant materials which can be used include BaxSr(zxe2x88x92x)TiO3 [BST], BaTiO3, SrTiO3, PbTiO3, Pb(Zr,Ti)O3 [PLZT], (Pb,La,Zr,Ti)O3 [PLZT], (Pb,La)TiO3 [PLT], KNO3, and LiNbO3. Unfortunately, most high dielectric constant materials are incompatible with existing processes and cannot be simply deposited on a polysilicon electrode as are presently utilized dielectric materials, such as Si3N4, SiO2/SiN4, and Si3N4/SiO2 composite layers. The incompatibility is a result of the O2 rich ambient atmosphere present during high dielectric constant material deposition or during annealing steps. The O2 oxidizes portions of the material used for the storage node plate.
U.S. Pat. No. 5,381,302 issued Jan. 10, 1995 to Sandhu et al. teaches methods for fabricating capacitors compatible with high dielectric constant materials wherein a storage node electrode is provided with a barrier layer, such as titanium nitride, which prohibits diffusion of atoms. A recessed conductive plug of polysilicon is deposited in a via, wherein a titanium layer is deposited on the conductive plug. A rapid thermal anneal is then performed to form a titanium silicide layer. The unreacted titanium layer is removed and a barrier layer is formed on the titanium silicide layer. A platinum layer is then deposited and patterned over the barrier layer, followed by a high dielectric constant layer which is followed by the deposition of a cell plate (preferably platinum) to form the capacitor. Although a high dielectric constant capacitor is formed, the capacitor has a low (i.e., relatively small) surface area. Furthermore, if the platinum layer is not properly patterned (i.e., misaligned) such that the barrier layer is exposed, oxidation of the barrier layer, the titanium silicide layer, and the conductive plug may occur.
Although the formation of high dielectric constant capacitors is known, forming such high dielectric constant capacitors with relatively large surface area structures, such as fins and cylinders, to further increase their storage capacitance is not feasible. This infeasibility may be attributed to an electric field which forms when the capacitor is in operation. If a thin structure, such as a fin, is formed in an effort to increase surface area, this electric field becomes particularly intense at the corners or edge of the thin structure. This intense electric field can break down the dielectric material, which breakdown can result in capacitor failure.
Therefore, it would be advantageous to develop a technique for forming a relatively large surface area, high dielectric constant capacitor, and RAM chips, memory cells, and capacitors employing same, while using inexpensive, commercially-available, widely-practiced semiconductor device fabrication techniques and equipment without requiring complex processing steps.
The present invention includes a novel memory cell capacitor and techniques for the formation of the memory cell capacitor which allow for, and promote, utilization of the advantages of relatively large surface area structures and high dielectric constant materials. The present invention utilizes a buffer material as a cap on the edge surfaces of the relatively large surface area structures to dampen or eliminate the intense electric field which is generated at the edge surfaces of the relatively large surface area structures during the operation of the capacitor.
The method of the present invention is practiced after the formation of an intermediate structure comprising transistor gates on a silicon substrate which has been oxidized to form thick field oxide areas and which has been exposed to implantation processes to form drain and source regions. The intermediate structure further comprises at least one barrier layer which covers the transistor gates and the silicon substrate.
The method of the present invention comprises patterning a first resist layer on the barrier layer, which is then etched to expose the drain regions in the substrate, forming vias. The resist layer is then stripped and a layer of conductive polysilicon material is applied over the structure to fill the vias. The polysilicon material is etched such that it is recessed within the vias. If oxidation of the polysilicon material during subsequent processing steps is a problem, a shield material may be applied and spacer etched to form a shield layer between the polysilicon material and the gates, and the barrier layer.
A layer of metal is applied over the structure. The structure is then heated, which causes a silicide reaction wherever the metal layer contacts the polysilicon material to form a metal silicide layer within the vias. The unreacted portion of the metal layer is then selectively removed, leaving the metal silicide layer covering the polysilicon material.
A metal barrier layer is applied over the metal silicide layer and the barrier layer. The metal silicide layer and metal barrier layer prevent the out diffusion of silicon from the polysilicon material (during subsequent heat steps) into a cell node which is to be formed above the metal barrier layer.
A resist layer is then applied over the metal barrier layer to substantially fill the vias. The resist layer is then etched such that plugs of the resist layer remain in the vias. The metal barrier layer is then etched to form a bottom contact adjacent the metal silicide layer. The resist plugs are then stripped away.
A layer of conductive material is deposited over the barrier layer and into the vias, thereby substantially filling the same, to contact the bottom contact. The conductive material is then patterned and etched to form electrically isolated, individual storage nodes which have relatively large surface area structures. These relatively large surface area structures can take the form of walls, columns, pins, annular circles, wedges, cones, or any such shape. A common element of each of these relatively large surface area structures is that each of them will have a relatively thin edge portion, surface, or shape edge where the conductive material is patterned. The material used to pattern the conductive material may be left on these edge portions or a buffer material may be added to these edge portions by any known techniques to form a cap on the edge portions.
One embodiment of etching conductive material comprises depositing a layer of oxide material over the conductive material layer. A resist layer is patterned and the oxide material is etched to form an opening, preferably circular, and to expose portions of the conductive material layer. Preferably, one edge of each opening is substantially centered in the center of the underlying polysilicon material.
The patterned resist layer is stripped and a mask material layer is deposited over the etched oxide material and the exposed conductive material layer. The mask material layer is then etched to form spacers. The etched oxide material is etched to leave the spacers free-standing. The pattern of the spacers is transferred down through the conductive material layer, and, preferably, into a portion of the barrier layer to form at least one relatively large surface area structure, such as a fin, in the conductive material layer. The transfer of the spacer pattern results in the conductive material layer forming electrically isolated, individual storage nodes with the spacers remaining on the edge portions of the relatively large surface area structure as the buffer material to form the cap.
After the relatively large surface area structures are formed with the cap on the edge portions thereof, a layer of high dielectric constant material is deposited over the etched structure. The capacitors are completed by depositing an upper cell plate, preferably platinum, over the high dielectric constant material.